This invention relates generally to semiconductor technology and, more specifically, to a gate oxide formed through local oxidation of silicon (LOCOS) to provide a MOS transistors with a large drain to gate breakdown voltage for electrostatic discharge (ESD) protection.
MOS technology, especially submicron CMOS integrated circuits (ICs), is susceptible to damage due electrostatic discharge at the input ports of the devices. A charge generating a 4000 volt pulse for a period of several nanoseconds is sufficient to damage a typical MOS device. Such a charge is easily accumulated on the human body in ordinary conditions. Voltage pulses of even 100 volts have been known to damage circuits. These gate voltages generate large electric fields between the gate and channel region underlying the gate. The intervening thin layer of gate oxide is often damaged from the resulting "punch-through" effect. As a result of the susceptibility of these devices to ESD, many MOS devices incorporate protection features.
A variety of ESD protection schemes have been used to protect MOS input ports. FIG. 1 illustrates an electrical circuit 10 including an input port 12 operatively connected to a MOS transistor 14 through an ESD protection circuit (prior art). The ESD protection circuit consists of a series current limiting element 16 and a network of shunt voltage clamps 18, 20, 22, and 24. Series resistors have been used for current limiting element 16. Diodes and silicon controlled rectifiers (SCRs) have been used for voltage clamps 18, 20, 22, and 24. Series resistor 16 de-couples the voltage seen at port 12 from the gate (g) of transistor 14. Diodes and SCRs 18, 20, 22, and 24, on either end of series resistor 16 tend to clamp the node voltage to a maximum level. However, the time constants associated with elements 16, 18, 20, 22, and 24 reduce the signal speed of intended signals and limit the reaction time of the protection circuits.
The simplest shunt circuit for ESD protection would be a single MOS transistor. However, to effectively discharge ESD input charges, such a device would have to exhibit a larger than normal drain to gate breakdown voltage and low drain breakdown voltage. In addition, the device would have a large threshold voltage and low parasitic capacitance, so that under normal conditions, the protection transistor does not add significant propagation delays to an intended incoming signal. SCRs typically turn on at relatively large voltages with relatively long delays. Therefore, an SCR cannot be used to protect sub-micron CMOS circuits without additional bias circuitry. An SCR that turns on at low trigger voltages is fairly complex circuit that is cumbersome to fabricate.
It would be advantageous if a simple voltage clamp, having a single channel area, could be developed to simplify fabrication and minimize the number of RC time constants. Further, it would be advantageous if an MOS transistor could be used to protect the input port of an MOS IC from ESD.
It would be advantageous if the drain to gate breakdown voltage of a MOS transistor could be increased for use as an ESD protection voltage clamp. Further, it would be advantageous the drain to gate breakdown voltage of a MOS transistor could be increased for ESD protection without increasing the drain voltage characteristics for all the MOS transistors in the IC.
It would be advantageous if the drain to gate breakdown voltage of a MOS transistor could be increased for use as a shunt voltage clamp for ESD protection without slowing the switching speed of the transistor.
Accordingly, a MOS device, having a large drain to gate breakdown voltage for ESD protection, selected from the group consisting of NMOS and PMOS transistors, is provided. The MOS device comprises source and drain regions of doped silicon, formed in a doped silicon well. The MOS device further comprises a local area of oxidized silicon (LOCOS) overlying the doped silicon well to form a thick region of gate oxide adjoining the drain. The LOCOS area has a thickness in the range between 2000 and 5000 .ANG., and the length of the LOCOS area is less than approximately 1 micron. A thin area of oxide overlies the doped silicon well forming a thin region of gate oxide adjoining the source. The thin gate oxide thickness is dependent upon the dielectric constant of the gate oxide material, the gate oxide thickness increasing as the dielectric constant increases. As a basis for comparison, when the gate oxide is thermally grown silicon oxide, then the gate oxide thickness is less than approximately 20 nanometers.
Further, a doped gate electrode partially overlies the thin gate oxide, and partially overlies the thick LOCOS gate oxide regions. The above-mentioned transistor has a large drain to gate breakdown due to the large region of oxide separating the drain from the gate. The ESD event turn-on time is short, comparable to a state of the art thin gate oxide transistor, because to electric field in the channel area next to the source is still susceptible to small changes in gate voltage.
The MOS device also comprises gate sidewalls made from either oxide or nitride, adjoining the gate electrode, and a dielectric interlevel made from oxide or TEOS overlying the gate, source, and drain. Contact holes through the dielectric interlevel access the gate, source, and drain regions, and metal in the contact holes forms metal connections to the gate, source, and drain. The metal connections electrically interface to the active areas of the MOS transistor in preparation for connections to other metal levels in the MOS device.
When the LOCOS device is NMOS, the silicon well is p doped, the source and drain are n+ doped, and the gate electrode is n+ doped. When the LOCOS device is PMOS, the silicon well is n doped, the source and drain are p+ doped, and the gate electrode is either p+ or n+ doped, although a p+ doped gate is more typical.
In the fabrication of a MOS device for ESD protection, selected from the group consisting of NMOS and PMOS transistors, a method for forming a LOCOS transistor with a large drain to gate breakdown voltage is also provided. The method comprises the steps of:
a) forming a well of silicon including a first dopant, from which source and drain regions are subsequently formed;
b) forming a localized area of oxidized silicon (LOCOS) having a first thickness;
c) depositing a thin layer of gate oxide having a second thickness overlying the doped silicon well and the LOCOS area; and
d) depositing, patterning, and doping, with a second dopant, a layer of polysilicon overlying a portion of the LOCOS area and an adjoining area of thin oxide, to form a gate electrode having a gate electrode length. The gate electrode is formed over both thin and thick areas of gate oxide.
The two-level gate oxide level formed through LOCOS permits the associated MOS transistor to develop higher than normal voltages on the drain before gate oxide breakdown occurs. Once the drain breakdown occurs, the parasitic bipolar transistor effect completes the turn-on of the MOS transistor, so that a low resistance between the drain and source results, and large currents are conducted. Such a device is ideally suited as a voltage clamp, since the low resistance and high current carrying capabilities of the device act to reduce the peak electrical charges at the drain. In this manner, circuitry connected to the drain of the LOCOS MOS transistor is protected from large energy spikes.